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preliminary data sheet november 2000 T8531/t8532 multichannel programmable codec chip set features n single 5 v power supply operation n per-channel programmable transmit gain 25.6 db range, better than 0.01 db steps n per-channel programmable receive gain 17.8 db range, better than 0.01 db steps n per-channel programmable hybrid balance n programmable termination impedances n programmable m -law, a-law, or linear pcm output n dtmf generator n dtmf receiver n caller id generator n call progress tones generator n automatic gain calibration n programmable time-slot assignment with bit offset n low-noise, balanced, receive slic interface n few or no slic/codec interface components required n analog and digital loopbacks n sigma-delta converters with dither noise reduction n serial microcontroller control interface n available in 64-pin mqfp and tqfp packages general description the multichannel programmable codec chip set is comprised of the T8531 16-channel line card signal processor and one or two custom t8532 octal a/d and d/a converters. a rom-coded tone plant is included on the signal processor. together these devices achieve a highly integrated and highly pro- grammable multichannel voice codec solution. software is provided to compute the gain and filter coefficients required to program the codec. 5-3793f (f) figure 1. system block diagram t8532 octal a/d d/a t8532 octal a/d d/a T8531 digital signal processor vtx (8) vrp (8) vrn (8) vtx (8) vrp (8) vrn (8) 2 3 2 3 ck16 vrtx (8) vrtx (8) pcm interface microprocessor interface asic
2 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable table of contents contents page features ..................................................................... 1 general description.................................................... 1 t8532 description.................................................... 4 T8531 description.................................................... 5 pin information ........................................................... 7 chip set functional description ............................... 12 transmit path......................................................... 12 antialias filter and s - d converter ...................... 12 decimator ........................................................... 12 digital transmit gain adjustment........................ 12 band filtering ...................................................... 12 m -law, a-law, and linear pcm modes............... 12 receive path ......................................................... 13 receive path filtering ......................................... 13 digital receive gain............................................ 13 interpolator and digital sigma-delta modulator.......................................................... 13 decoder, filters, and receive amplifier ............. 13 other chip set functions....................................... 13 voltage reference............................................... 13 hybrid balance .................................................... 13 analog termination impedance synthesis.......... 13 digital termination impedance synthesis ........... 13 loopback modes ................................................. 14 interchip control interface ................................... 14 T8531 functional blocks........................................ 14 clock synthesizer................................................ 14 dsp clock frequency selection ......................... 14 T8531 system interface ..................................... 15 T8531 microprocessor interface.......................... 15 t8532 octal control interface ............................. 16 T8531 time-slot assignment (tsa).................... 16 dsp engine timing................................................ 16 T8531 program structure.................................... 16 control of the dsp engine via the microprocessor interface .................................. 17 the dsp engine time-slot information tables ............................................................... 17 the dsp engine ac path coefficient table ........ 17 the time-slot control word................................ 18 operations performed by the dsp engine at T8531 start-up ................................................. 18 microprocessor start-up of the dsp engine....... 19 powering up a time slot in the T8531................ 19 disabling a time slot in the T8531 ..................... 19 t8532 powerup/powerdown ............................... 19 changing dsp ram space of an active time slot........................................................... 20 dsp engine memory requirements ................... 20 contents page T8531 reset and start-up ..................................... 20 hardware reset .................................................. 20 internal reset ...................................................... 21 reset of the t8532 devices ................................ 21 start-up after internal reset.................................. 21 autocalibration..................................................... 22 tone plant.............................................................. 22 dtmf transceiver............................................... 22 caller line identification ...................................... 22 call progress tones............................................ 22 absolute maximum ratings...................................... 23 handling precautions ............................................... 23 electrical characteristics .......................................... 24 dc characteristics .................................................. 24 transmission characteristics ................................... 25 timing characteristics .............................................. 29 software interface .................................................... 32 applications .............................................................. 42 common voltage reference.................................. 45 outline diagrams...................................................... 46 64-pin mqfp ......................................................... 46 64-pin tqfp .......................................................... 47 ordering information................................................. 48 appendix a. transmit path group delay vs. bit offset ................................................................ 48 figures page figure 1. system block diagram .................................1 figure 2. block diagram of t8532 octal converter.....4 figure 3. block diagram of one t8532 analog channel........................................................4 figure 4. T8531 block diagram...................................5 figure 5. T8531 digital ac path ...................................6 figure 6. control, pcm, and octal interfaces..............6 figure 7. t8532 64-pin mqfp ....................................7 figure 8. T8531 64-pin tqfp .....................................9 figure 9. timing characteristics of pcm interface assuming 2.048 mhz sck rate ................30 figure 10. timing diagram for microprocessor write/read to/from the dsp on the control interface.......................................31 figure 11. line card solution using the l7585 slic .........................................................42 figure 12. line card solution using the l9215g slic .........................................................43 figure 13. line card solution using the l9310g slic .........................................................44 figure 14. common 2.4 v voltage reference...........45
preliminary data sheet november 2000 lucent technologies inc. 3 codec chip set T8531/t8532 multichannel programmable table of contents (continued) tables page table 1. t8532 pin descriptions ................................. 8 table 2. T8531 pin descriptions ............................... 10 table 3. active time-slot spacing in a pcm bus frame ................................................... 15 table 4. dsp engine ram map for channel_0 ac path coefficients ......................................... 17 table 5a. bit map for dsp engine time-slot control word............................................. 18 table 5b. bit map for default per-board coefficient tables...................................... 18 table 6. dsp engine ram map for time-slot information table 0...................................... 18 table 7. summary of microprocessor commands for control of T8531 data processing ......... 20 table 8. digital interface............................................ 24 table 9. analog interface .......................................... 24 table 10. t8532 power dissipation...........................25 table 11. T8531 power dissipation...........................25 table 12. gain and dynamic range ......................... 25 table 13. noise (per channel) ..................................27 table 14. distortion and group delay ....................... 28 table 15. crosstalk.................................................... 28 table 16. pcm interface timing ............................... 29 table 17. serial control port timing ........................ 31 table 18. dsp engine ram memory map ................ 32 table 19. T8531 time-slot assignment memory map ...........................................................34 table 20a. bit map for T8531 time-slot assignment registers at 0x14000x140f................. 34 table 20b. bit map for ctz disable and null channel................................................... 34 table 21. T8531 channel register memory map for t8532 device 0 ................................... 35 table 22. T8531 channel register memory map for t8532 device 1 ................................... 35 table 23. bit map for t8532 powerup/powerdown registers at 0x15000x1507 and 0x15400x1547 ....................................... 35 table 24. bit map for t8532 channel control register 1 at 0x15080x150f and 0x15480x154f .......................................36 table 25. t8532 control register 1: transmit gain ...........................................................36 table 26. t8532 control register 1: analog termination impedance.............................36 table 27. t8532 control register 1: digital loopback ...................................................37 table 28. bit map for t8532 all channel test register at 0x1510 and 0x1550.................37 table 29. bits 3:0 of t8532 all channel test register at 0x1510 and 0x1550.................37 table 30. bit map for t8532 channel control register 2 at 0x15180x151f and 0x15580x155f .......................................38 table 31. t8532 control register 2: receive gain ...38 table 32. T8531 control register map .....................38 table 33. bits 15:8 of T8531 board control word 1 at 0x1ffe ..................................................39 table 34. bits 7:0 of T8531 board control word 1 at 0x1ffe ..................................................39 table 35. bits 15:9 of T8531 board control word 2 at 0x1ffc..................................................40 table 36. bits 8:0 of T8531 board control word 2 at 0x1ffc..................................................40 table 37. bits 15:0 of T8531 board control word 3 at 0x1ffa ..................................................40 table 38. bits 15:0 of T8531 board control word 4 at 0x1ff8 ..................................................40 table 39. bits 15:0 of T8531 board control word 5 at 0x1ff6 ..................................................40 table 40. bits 15:0 of T8531 reset of microprocessor commands at 0x7fff .....40 table 41. dsp engine rom memory map................41 table 42. transmit path group delay vs. bit offset ..48
4 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable general description (continued) t8532 description the t8532 block diagram is shown in figure 2. each of its eight channels consists of an antialias filter, sigma-delta a/d and d/a converters, reconstruction and smoothing filters, termination impedance synthesis, and selectable gain. the digital oversampled data is multiplexed onto a serial data port designed to interface with the T8531. another serial interface accepts control data from the T8531 for activating the various gain settings, self-test, and powerdown modes. this chip also contains a precision voltage reference. 5-3794.b (f) figure 2. block diagram of t8532 octal converter 5-3796.d (f) * antialiasing filter. figure 3. block diagram of one t8532 analog channel 8-channel a/d d/a analog hybrid & termination voltage reference oversampled data interface control interface vtx[7:0] vrtx[7:0] vrp[7:0] vrn[7:0] v dda v ssa v dd v ss osdx[1:0] osdr[1:0] osck osfs cdo cdi ccs rstb gain aaf* ? - d a/d a t gain sum gain v references receive filter d/a d/a vtx vrp vrn 1.024 mhz 1.024 mhz vrtx digital loopback
lucent technologies inc. 5 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable general description (continued) T8531 description as shown in figure 4, the T8531 contains a digital signal processor (dsp) engine surrounded by a customized input/output frame. the i/o frame performs the m -law or a-law conversion as well as the decimation and interpola- tion functions needed to interface the sigma-delta bit streams to the digital signal processor engine. the sigma- delta converters operate at a 1.024 mhz sample rate, while the signal processor operates at 16 ksamples/s. a key function of the i/o frame is to control the timing of the digital data going to the signal processor so that group delay is minimized. the i/o frame also contains an integrated phase-locked loop which synthesizes all the required internal clocks for the chip set. the microcontroller interface is used to run the rom routines and to download the gain, filter, and balance network settings, powerup/powerdown commands, time-slot assignments, digital loopback settings, and commands for the t8532 octal chips. 0505(f) figure 4. T8531 block diagram pll clock synthesizer jtag system pcm interface data transfer m /a-law converter micro- processor control interface dsp rom dsp ram digital signal processing engine decimator interpolator tsa t8532 control interface t8532 oversampled interface upck updi updo tstclk v dd v ss hds upcs highzb rstb t_sync test osdx/r[3:0] osck osfs cdo ccs0 ccs1 cdi tdi tck tms tdo stsxb sdx sdr sck sfs v dda v ssa ck16
6 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable general description (continued) T8531 description (continued) 0498 (f) figure 5. T8531 digital ac path 5-4229.d (f) figure 6. control, pcm, and octal interfaces m /a-law to linear recv filter rel rdg inter- polator digital ? - d balance filter linear to m /a-law xmt filter rel tdg ? decimator ? 64 1.024 mhz 8 khz pcmrx 8 khz pcmtx 1.024 mhz abs rdg abs ctz filter ? m /a-law to linear recv filter rel rdg inter- polator digital ? - d balance filter linear to m /a-law xmt filter ? decimator ? 64 1.024 mhz 8 khz pcmrx 8 khz pcmtx 1.024 mhz abs rdg tdg ctz filter ? osfs osck osdr0 osdr1 osdx0 osdx1 cdo cdi codec 0 t8532 dsp T8531 8 khz sync 4 mhz clock 4 ch rx data 4 ch rx data 4 ch tx data 4 ch tx data chip select control register control register upck upcs updi updo clock chip select control register in control register out sck sfs sdr sdx stsxb data transmit clock frame sync data receive backplane codec 1 t8532 chip select osdx2 osdr2 osdr3 osdx3 pcm interface control interface octal interface osdx2 osdr2 osdr3 osdx3 cdo cdi osck osfs 4 ch rx data 4 ch rx data 4 ch tx data 4 ch tx data osfs osck osdr0 osdr1 osdx0 osdx1 cdi cdo ccs0 ccs1 ccs0 ccs1 driver enable micro- processor pcm bus
lucent technologies inc. 7 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable pin information 5-9214 (f) figure 7. t8532 64-pin mqfp 60 59 58 57 56 55 54 53 52 61 rstb osdx0 vtx0 v ddd ccs osdr1 v ssd vtx7 osck 62 63 64 51 50 49 cdi osdr0 v dda cdo osdx1 v dda osfs 30 28 27 26 25 24 23 22 21 20 29 nc v dda vrtx4 v dda v ssa nc vtx3 vrtx3 nc 31 32 19 18 17 nc nc vtx4 nc nc v dda nc 13 12 11 10 9 8 7 6 5 4 vrtx6 vrtx5 vrtx7 vrn7 vrn6 v ssa vrp4 v dda 14 15 16 3 2 1 vrp6 vtx5 vrp7 v ssa vrp5 vrn5 vrn4 vtx6 36 38 39 40 41 42 43 44 45 46 37 vrp1 vtx2 vrtx0 vrp0 v ssa vrp2 v ssa vrp3 vtx1 35 34 33 47 48 vrn1 v dda vrn0 vrtx2 vrn2 vrn3 vrtx1 t8532 osdx0
8 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable pin information (continued) table 1. t8532 pin descriptions note: ti = ttl input, to = ttl output; ci = cmos input, co = cmos output; ai = analog input, ao = analog output; i u indicates a pull-up device is included on this lead, i d indicates a pull-down device is included on this lead. number name type name/function 64, 8, 10, 18, 31, 39, 41, 49 vtx[7:0] ai analog input. transmit signal voltage to be encoded. 1, 7, 11, 17, 32, 38, 42, 48 vrtx[7:0] ai transmit reference voltage. 2.4 v reference. each pin must have a sep- arate supply associated with the corresponding vtx pin. 2, 6, 12, 16, 33, 37, 43, 47 vrp[7:0] ao noninverting receive output. this pin can drive high-impedance loads either differentially or single ended. it is the complement of the vrn output. 3, 5, 13, 15, 34, 36, 44, 46 vrn[7:0] ao inverting receive output. this pin can drive high-impedance loads either differentially or single ended. it is the complement of the vrp output. 9, 19, 27, 30, 40, 50, 63 v dda 5 v analog power supply. power supply decoupling capacitor (0.1 m f) should be connected from each v dda pin to analog ground. capacitors should be located as close as possible to the device pins. 4, 14, 21, 35, 45 v ssa analog ground. 51 v ddd 5 v digital power supply. decouple with a 0.1 m f capacitor to digital ground. 62 v ssd digital ground. 60, 59 osdx[1:0] co oversampled transmit data. four channels of 1.024 mhz s - d transmit data is transmitted to the T8531 through each of these pins. the data rate is 4.096 mhz. 61, 58 osdr[1:0] ci oversampled receive data. four channels of 1.024 mhz s - d receive data is received from the T8531 on each of these pins. the data rate is 4.096 mhz. 57 osck ci interface clock. the 4.096 mhz clock that enters this pin from the T8531 serves as the bit clock for all the oversampled data transmission between this chip and the T8531. this is the master clock input for the t8532. 56 osfs ci interface frame sync. this signal serves as the frame sync for the over- sampled data interface between the t8532 and the T8531. 54 cdi ci control data interface input. the T8531 sends control register address and data to the t8532 through this pin. one address byte and one data byte are accepted each time ccs is toggled. 52 cdo co control data interface output. control register contents are clocked out through this pin. 53 ccs ci control interface chip select (active-low). this active-low input enables the control interface. 55 rstb ti u reset (active-low). this input must be pulled high for normal operation. when pulled momentarily low (at least 1 m s) while osck is active, all pro- grammable registers in the device are reset to the states specified under powerup initialization. this pin has an internal pull-up resistor. 20, 2226, 28, 29 nc no connect. no connection to chip. these pins can be used as logic level tie points.
lucent technologies inc. 9 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable pin information (continued) 5-9213 (f) figure 8. T8531 64-pin tqfp 60 59 58 57 56 55 54 53 52 61 t_sync highzb v ss cdi ccs1 ck16 v dd dspcksl1 v ss 62 63 64 51 50 49 cdo rstb v dd ccs0 test v ss v dd 30 28 27 26 25 24 23 22 21 20 29 sdx upck scksel v dd sfs updi v dd v ss v dd 31 32 19 18 17 sdr v ss v ss sck upcs updo stsxb 13 12 11 10 9 8 7 6 5 4 tck v dda dspcksl2 v dd tdo nc v dd v ss 14 15 16 3 2 1 tms v dd v ss tdi nc v ssa v ss tstclk 36 38 39 40 41 42 43 44 45 46 37 osdx3 osck jtestb v ss osdx2 osdr0 osdr1 v ss v ss 35 34 33 47 48 osdr2 osfs v dd osdx0 osdx1 v dd osdr3 T8531
10 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable pin information (continued) table 2. T8531 pin descriptions note: ti = ttl input, to = ttl output; ci = cmos input, co = cmos output; ai = analog input, ao = analog output; i u indicates a pull-up device is included on this lead. number name type name/function 29 updi ti control data interface input. the microcontroller sends control register address and data to the T8531 through this pin. 30 updo to control data interface output. the microcontroller receives control regis- ter contents from this pin. inactive state is high impedance. 27 upck ti control data interface clock. bit clock for the control interface. speed is limited to 4.096 mhz. 28 upcs ti control interface chip select (active-low). this active-low input enables the control interface. 43, 45, 36, 38 osdx[3:0] ci oversampled transmit data. four channels of 1 msamples/s s - d transmit data are received from the t8532 chips through each of these pins. the data rate is 4.096 mhz. 42, 44, 35, 37 osdr[3:0] co oversampled receive data. four channels of 1 msamples/s s - d receive data is transmitted to the t8532 chips on each of these pins. the data rate is 4.096 mhz. 39 osck co 4.096 mhz clock. clock for data transfer to/from t8532 chips. 40 osfs co oversampling sync. 8 khz synchronization pulse for data transfer to/from t8532 chips. 11 v dda synthesizer v dd . power supply for clock synthesizer block. 13 v ssa synthesizer ground. ground connection for the clock synthesizer block. 24 stsxb to backplane drive enable (active-low). active when sdx is transmitting valid data; high impedance otherwise. this pin provides an enable signal for a backplane line driver. 20 sck ti master clock input. this is the bit clock used to shift data into and out of the sdr and sdx pins. it is the input to the clock synthesizer and is used to generate all internal clocks. rate is 4.096 mhz. 17 scksel ti u master clock select input. a logic low selects the 2.048 mhz sck. a logic high selects the 4.096 mhz sck. an internal pull-up device is included, pro- viding 4.096 mhz sck operation with no external connections. 22 sdr ti receive pcm input. the data on this pin is shifted into the T8531 on the falling edges of sck. data is only entered for valid time slots as defined in the tsa registers.
lucent technologies inc. 11 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable pin information (continued) table 2. T8531 pin descriptions (continued) * the dsp is not configured for boundary-scan operation. note: ti = ttl input, to = ttl output; ci = cmos input, co = cmos output; ai = analog input, ao = analog output; i u indicates that a pull- up device is included on this lead, i d indicates that a pull-down device is included on this lead. number name type name/function 23 sdx to transmit pcm output. this pin remains in the high-impedance state except during the transmit time slots as defined in the tsa registers. data is shifted out on the rising edge of sck. 21 sfs ti frame sync. active-high pulse or square wave with an 8 khz pulse repetition rate. the rising edge defines the start of the transmit and receive frames. 54 cdo co t8532 control data output . control register information for the t8532 chips. data is valid only when either ccs0 or ccs1 is low. 51 cdi ti u t8532 control data input . control register information from the t8532 chips. data is valid only when either ccs0 or ccs1 is low. an internal pull-up device is provided. 53, 52 ccs [1:0] co control interface chip select (active-low). these active-low outputs select one of the associated t8532 chips. 7tckti jtag test port * common test clock. rate 20 mhz. 4tditi u jtag test port * serial data input. a pull-up device is provided. 5tdoto jtag test port * serial data output. 6tmsti u jtag test port * mode select. a pull-up device is provided. 48 jtestb ti u jtag test. used for factory testing. do not make any connection to this pin. a pull-up device is provided. 59 highzb ti u 3-state control pin (active-low). when pulled low, the device output pins go into a high-impedance state. a pull-up device is provided. 60 test ci u test mode input (active-low). this input allows bypass of clock synthe- sizer and uses tstclk to drive the chip. a pull-up device is provided. 61 ck16 co 16 mhz clock output. 16.384 mhz clock output (50% duty cycle). note that this clock divides down to a lower frequency (dependent upon the dspcksl setting) when the T8531 is in hardware reset. the frequency of ck16 is unaffected by software reset. 8tstclkci test clock. 12, 14 nc no connect. this pin may be used as a tie point. 64 dspcksl1 ci d dsp clock select. see dsp clock frequency selection on page 14. 1 dspcksl2 ci d dsp clock select. see dsp clock frequency selection on page 14. 55 t_sync ci u test sync (active-low). used for factory testing. do not make any con- nection to this pin. a pull-up device is provided. 58 rstb ti u reset (active-low). a logic low initiates reset. a pull-up device is pro- vided. 3, 10, 16, 19, 25, 31, 34, 46, 50, 56, 62 v dd 5 v digital power supply. power supply decoupling capacitors (0.1 m f) should be connected from each v dd pin to ground. capacitors should be located as close as possible to the device pins. 2, 9, 15, 18, 26, 32, 33, 41, 47, 49, 57, 63 v ss digital ground.
12 12 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description transmit path antialias filter and s - d converter the line interface circuit must provide a transmit signal, vtx, and a reference voltage, vrtx, which is the dc voltage of the vtx signal for that channel. the input signal goes into a programmable-gain ampli- fier. the signal is then passed through an antialias filter followed by a s - d a/d converter. the s - d converter operates at 1.024 mhz. the processed output signals are multiplexed into two groups of four channels each onto output pins osdx[1:0], each of which operates at 4.096 mhz. a precision, on-chip voltage reference helps ensure accurate and highly stable transmission levels. it is important to understand the difference between how the gain levels should be set in the t8532 and how these levels would be set in a standard codec. the t8532 is best thought of as a data acquisition sys- tem, not a codec. hybrid balance, fine gain adjust, m - or a-law coding, filtering, and equalization are done after the a/d in the t8532 and by the dsp processor in the T8531. the analog gain adjust taps should not be used to set the absolute level at the pcm output. this can be done using the dsp gain adjust taps. the ana- log taps should be set so the signal at the input to the a/d converter is as close as possible to the full-scale input level of the a/d for the largest signal level that will be present at the vtx input. this optimizes the dynamic range of the a/d. the 0 db gain tap should thus be used if the maximum signal level is in the range between 2.25 vp-p and 3.2 vp-p. the 3 db tap should be used for signals with a maximum signal level in the range of 1.6 vp-p and 2.25 vp-p. the 6 db tap should be used for signals with a maximum signal level in the range between 1.1 vp-p and 1.6 vp-p. higher gain lev- els should be used for signals with smaller absolute levels. the signal level to produce a 0 dbm0 level at the digital transmit output of the T8531 is not a fixed quantity as explained above. for a line with a complex impedance or an rx echo signal, extra headroom must be allowed and the tx signal level must be set to account for the headroom. in this specification, the largest possible 0 dbm0 level for the tx signal is assumed. this guar- antees that the distortion specification will not be exceeded for all practical 0 dbm signal levels. the larg- est possible 0 dbm signal is one that has no headroom for tx gain equalization. for the case of 0 db transmit gain, this level is found as: (3.2 v/log C1 (3.15/20)) = 2.23 vp-p. this level is the worst-case 0 dbm0 level. decimator the decimator filters out the high-frequency compo- nents and down-samples to 16 khz. it also reorders the 16 channels of transmit signals into a sequence that is determined by the time-slot assignment. digital transmit gain adjustment the transmit absolute and relative gains are specified as 15-bit binary numbers representing their linear magnitude. these gains default to 4000 hex. this equates to a 0 db gain for the relative gain but equates to a 1.65 db gain for the absolute gain. for a 0 db gain, program the absolute gain for 34ed hex. gain can be varied from minus infinity db (off) (0000 hex) to 6 db for relative gain or to 7.65 db for absolute gain (7fff hex). the relative gain control allows for tlp adjustment without hybrid balance or termination coefficient modifi- cation. band filtering the bandpass filter in the transmit path removes power line and ringing frequencies, and eliminates most of the signal energy at 4 khz and above. this allows the encoder to transmit the filtered signal at 8 ksamples/s, the worldwide standard. the transmit filtering is implemented with a low-pass filter, followed by a high-pass filter. the data samples enter the filter at 16 ksamples/s. they are first low-pass filtered to 3.4 khz. after low-pass filtering, the sampling rate is reduced to 8 ksamples/s. the samples are then high-pass filtered to 300 hz. the low-pass filter also serves as an equalizer for fre- quency response alterations. a set of equalizer coeffi- cients that modify this filter are required for each complex termination impedance when using a voltage feed, current-sensed slic. m -law, a-law, and linear pcm modes in the transmit path, the 8 ksamples/s pcm signal out- put from the filter is processed prior to transmission over the system interface. the 16-bit linear pcm signal may be compressed according to either m -law or a-law, or transmitted as two consecutive 8-bit words. the selection is programmable via the microprocessor interface. please note, when using a-law, a linear value of 0 is always encoded as 7f.
lucent technologies inc. 13 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) receive path in the receive direction, the signal received from the system interface is converted to a 16-bit linear pcm sig- nal. receive path filtering the 16-bit linear pcm signal is filtered and interpolated to 16 ksamples/s to meet the receive signal loss charac- teristics. this filter smooths the data following interpola- tion from 8 ksamples/s to 16 ksamples/s. the filter can also serve as an equalizer for frequency response alter- ation. this is required for complex termination imped- ance cases when using a current feed, voltage-sensed slic. one of two receive filters can be used, the receive filter and the extended receive filter. the receive filter has two poles and three zeros. this filter can be used to minimize downloadable code (to use this receive filter, select the t7531x codec in the aquarium coefficient software). the extended receive filter provides more flexibility in coefficient optimization by providing three poles and three zeros. the aquarium coefficient soft- ware defaults to the extended receive filter when the T8531x codec is selected. digital receive gain the receive absolute and relative gains are specified as 15-bit binary numbers representing their linear magni- tude. these gains default to 4000 hex. this equates to a 0 db gain for the relative gain but equates to a C0.211 db gain for the absolute gain. for a 0 db gain, program the absolute gain for 4193 hex. gain can be varied from minus infinity db (0) (0000 hex) to 6 db for relative gain or to 5.8 db for absolute gain (7fff hex). the relative gain control allows for tlp adjustment with- out hybrid balance or termination coefficient modifica- tion. interpolator and digital sigma-delta modulator the sampling frequency of the receive signal from the digital gain adjustment is increased from 16 khz to 64 khz by the interpolator, which removes most of the high-frequency signal images above 8 khz. the interpo- lator also maps each of 16 time slots to the appropriate line channel through the digital sigma-delta modulator. the digital sigma-delta modulator converts the interpo- lated signal to a 1.024 mhz bit stream which is then sent to the t8532 device. decoder, filters, and receive amplifier receive data enters the t8532 on pins osdr[1:0] at 4.096 mhz; four channels are time-division multiplexed onto each pin. the data is demultiplexed into eight indi- vidual channels. the processed signal for each chan- nel passes through switched-capacitor d/a and reconstruct filters, followed by a smoothing filter. a pro- grammable gain amplifier is included, followed by an output amplifier capable of driving a 50 k w load to 1.58 v single-ended (relative to vos) or 3.16 v dif- ferential at peak overload. for single-ended operation, the load must be ac coupled to vrp (or vrn). other chip set functions voltage reference the t8532 has a precision on-chip voltage reference which ensures accurate and highly stable transmission levels. hybrid balance the hybrid balance function is provided as a digital block in the T8531. the T8531 implements a 9-tap fir and a single-pole iir digital balance filter in which a replica of the echo is digitally subtracted from the transmit plus near-end echo signal. the coefficients are user programmable on a per-line basis via the microprocessor interface. analog termination impedance synthesis termination impedance matching is implemented to maximize the power transfer capability at the loop inter- face and to minimize signal reflections between the transmit and receive paths. the resistive component, implemented in the t8532 device, comprises a variable attenuated path between vtx and vrp. the capacitive component is imple- mented in the digital domain. analog termination impedance (ati) is provided with 16 gain settings to match a voltage drive/current sense line interface circuit with the following characteristics: z t = 2r p + g tx * g rx * a t where z t is the termination impedance in ohms, r p is the resistance of each protection resistor (for stability r p 3 50 w ), g tx is the slic transmit gain, g rx is the slic receive gain, and a t is the t8532 feedback gain. the polarity of the a t gain is positive (positive voltage swing on vtx gives a positive voltage swing on vrp). the gain values are shown in table 26; gain tolerances are 2%. differential receive output is assumed. digital termination impedance synthesis the ctz filter in the T8531 synthesizes complex termi- nation impedances. the ctz filter utilizes alpha and beta coefficients (board control words 4 and 5, respec- tively) to perform the synthesis. one set of alpha beta coefficients is required for each termination impedance and balance network.
14 14 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) other chip set functions (continued) digital termination impedance synthesis (continued) alpha bits [9:0] represent the rc time constant of the impedance that the filter is going to synthesize. the bits are formatted as twos complement. alpha bits must be a nonzero value. beta bits [7:0] represent the dc gain of the filter. beta coefficients are also formatted as twos complement. setting beta equal to zero turns off the ctz function. there is a constraint on the value of the protection resistor with regard to termination impedance synthesis and hybrid balance. for synthesis to operate properly, the combined series resistance of the tip protection resistor and the ring protection resistor must be 100 w or greater. loopback modes there are four loopback modes in the t8532. the first two loopback modes are controlled by the all- channel test (act) register. act bits 0 and 1 place all eight channels into loopback mode. analog and digital loopback are described and shown in block diagram form in table 29. analog loopback allows one to check functionality from tip/ring up to and including the t8532. digital loopback allows the T8531 to check t8532 functionality. the third loopback mode is used in the autocalibration sequence (control register 2). this mode provides a loopback between a selected channel and channel four of a given t8532. the channel to be calibrated is selected via control register 1 (see table 27). channel four is the only channel in the t8532 that is trimmed for gain accuracy. every other channel uses channel four as a reference and is calibrated to it during the autocal- ibration sequence. the fourth loopback mode is a digital loopback mode located in control register 1. this operates like the digi- tal loopback mode described in the notes for the act register (table 29). unlike the act register, this digital loopback mode is selectable per channel. this loop- back mode can be used to check t8532 functionality from the T8531 device. it is also used during the cali- bration sequence. there is one loopback mode in the T8531. loopback at the oversampled data interface is controlled by board control word 1. this mode allows the T8531 to test itself. when bit 0 of 0x1ffe is selected, all 16 channels of octal interface receive data (osdrn) are looped back to the T8531 transmit inputs (osdxn). interchip control interface the control interface is a 4-pin interface used to send control information to the t8532 from the T8531, and to read back the control register contents. the pins con- sist of a chip select input (ccs0 /ccs1 ), a data input (cdi), and a data output (cdo). the transfer of control data is synchronous with the 4.096 mhz osck, which is also used for oversampled data transfer. T8531 functional blocks clock synthesizer the clock synthesizer block is a phase-lock loop (pll) circuit which takes sck supplied by the backplane and uses it to produce the dsp engine clock. the input clock, sck, can be 2.048 mhz or 4.096 mhz. an on-chip clock synthesizer has the advantages shown below: n precludes the need for extra clocks to be fed over the backplane. n constrains the high-speed dsp engine clock within the device. n synchronizes all clocks used on the line card to the backplane clock, thus reducing board noise due to beat frequencies. a clock generator block takes the pll output and divides it down to produce all the lower-frequency clocks used by the T8531 and t8532. two pins, dspcksl1 (pin 64) and dspcksl2 (pin 1), select the dsp1627s operating clock frequency as shown below. the default frequency is 49.152 mhz (e.g., no connection to pins 1 and 64). normal codec operations will perform at this frequency. for tone plant operation, 81.92 mhz must be used. dsp clock frequency selection dspcksl2 dspcksl1 dsp freq. (mhz) 0 0 49.152 0 1 65.536 1 0 81.920 1 1 93.304
lucent technologies inc. 15 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) T8531 functional blocks (continued) T8531 system interface the system interface is a full-duplex interface used for the exchange of pcm data with the system. the sys- tem is the master of this bus. no control information is transmitted over the system interface; all control instructions are routed over the microprocessor inter- face. the system interface is used for all 16 lines serviced by the T8531. the pcm data rate is 8 ksamples/s/line, so the total required channel capacity is 16 x 8 = 128 kwords/s in each direction. at the 4.096 mhz rate, each word takes 1.95 m s to transmit interleaved with 5.86 m s of dead time. the frame sync, sfs, is pre- sented to the system interface at an 8 khz rate. a single bit clock and frame sync are used to control both the transmit and receive directions. the beginning of the first time slot in a frame is identified from the sfs input (see figure 9). in nondelayed mode, sfs is active coincident with bit 0 of time slot 0 of the rx frame (and the tx frame if the programmed offset between tx and rx is 0). in delayed mode, sfs is active one cycle earlier. the amount of skew or offset between the transmit and receive frames and time slots is programmable via board control word 2, 0x1ffc. the bit offset is up to a frame, i.e., up to 511 bits in 4 mhz mode. the bit offset skew takes place in the system pcm interface block. the active transmit and receive time slots are deter- mined by the card address. the number of time slots within a frame varies according to the rate of sck. only 16 time slots are ever active in a frame, as shown in table 3. the T8531 obtains its card address in board control word 1, 0x1ffe. in m -law or a-law mode, each pcm word is only 8 bits long and occupies one time slot. in linear mode, the pcm word is 16 bits long and occupies two adjacent time slots. the msb is the first bit clocked out in the valid time slot, and the lsb is the last bit of the follow- ing (invalid) time slot. T8531 microprocessor interface this interface between the microprocessor (or other external controller) and the T8531 device carries user- supplied program variables and control and test instructions to both the T8531 and the t8532 octal converters. the external device is the master of the microprocessor interface. the interface is serial and asynchronous, and consists of four pins (upck, upcs , updi, updo). the data rate is determined by the customers choice of external device, but may not exceed 4.096 mhz. microprocessor interface com- mands consist of two words, address and data. address and data are 16 bits wide. the T8531 expects an address first. the first bit of the address word is the r/w flag, which tells the T8531 whether it must receive or send data (receive, r/w = 0; send, r/w = 1). addresses less than 0x1400 refer to the dsp engine ram space. if a read from the dsp engine is required, the microprocessor interface issues a read interrupt to the dsp engine. if it's a write to the dsp engine, the microprocessor interface shifts in the data word and saves it into the data register before sending a write interrupt to the dsp engine. once in every 7.8 m s time segment, the dsp engine checks whether an interrupt is outstanding from the microprocessor interface block. if so, the dsp engine reads the address register. if it's a read, the dsp engine fetches the word from ram, places it in the data register, and shifts it out to the microprocessor. if it's a write, it puts the contents of the data register into ram. table 3. active time-slot spacing in a pcm bus frame sck rate (mhz) total # of time slots card address valid time slots invalid time slots 2.048 32 0 1 0, 2, 4, . . . 30 1, 3, 5, . . . 31 1, 3, 5, . . . 31 0, 2, 4, . . . 30 4.096 64 0 1 2 3 0, 4, 8, . . . 60 1, 5, 9, . . . 61 2, 6, 10, . . . 62 3, 7, 11, . . . 63 13, 57, . . . 6163 0, 24, 68, . . . 6263 01, 35, 79, . . . 63 02, 46, 810, . . . 6062
16 16 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) T8531 functional blocks (continued) a pause therefore exists between the external control- ler issuing an address and receiving a data read back. the data rate of 2.048 mhz allows 256 sck cycles in a frame, i.e., eight address/data pairs with no pause between words. since the dsp engine can process only one interrupt every 7.8 m s, the T8531 requires a separation between address and data on read and write instructions to the microprocessor interrupt (see figure 10). this, in effect, requires upck to be gapped. addresses 3 0x1400 refer to registers or tsa ram external to the dsp engine. if the address word from the microprocessor is 0x1400 through 0x140f, it activates the tsa state machine. if the address word from the microprocessor is 0x1500 through 0x15ff, it activates the t8532 control state machine. microprocessor data and address words can be flushed out of the T8531 by addressing 0x7fff with data word 0xffff (see table 40). t8532 octal control interface the two t8532 chips cannot be accessed by the micro- controller directly; the t8532's registers are all accessed via the T8531 microprocessor interface. the microprocessor communicates serially with the t8532 by simply writing or reading 16-bit address and 16-bit data. the octal control interface block translates this address and data into 8-bit address and 8-bit data needed by the t8532. the octal control interface block waits until the microprocessor interface block receives all 16 bits of the address word and determines whether this is a read or write operation by looking at bit 15. if this is a write operation for a t8532 chip, it receives another 16-bit data word. T8531 time-slot assignment (tsa) the tsa block contains a 16 x 6 dual-port ram which is readable or writable via the microprocessor inter- face. table 18 gives the bit map for tsa ram words. the tsa ram is in time-slot order, i.e., location 0x1400 is for time slot 0 and 0x1401 for time slot 1 and so on. the low 4 bits (b3b0) indicate which of the 16 possible channel numbers is assigned to this time slot. the time-slot assignment is controlled by the micropro- cessor writing to address 0x1400 through 0x140f. the tsa block also generates the control signals and flags used to synchronize the tsa, interpolator and decimator, and t8532 interface blocks. the tsa ram is not preinitialized, so the microprocessor is required to write to all 16 locations of the tsa ram at start-up to ensure proper operation. twice a frame, the tsa state machine reads the entire tsa ram from top to bottom in sequence and sends the contents of each ram loca- tion to the interpolator as channel numbers for rx channels. the tsa state machine performs the same procedure for the decimator to provide it with the tx channel numbers. by performing tsa at the oversam- pled sigma-delta rate, round trip group delay is signifi- cantly minimized. dsp engine timing the dsp engine processes all 16 lines every frame. in order to simplify synchronization of data exchanges, the processing frame is broken into 16 equal time seg- ments of 7.8 m s each. the rom code is identical for each time segment. synchronization between the engine and the rest of the chip is enforced by the system interface block, which issues an interrupt every 7.8 m s. this interrupt is the only unmasked interrupt processed by the engine. the interrupt service routine forces the rom code to branch to the start of the processing loop. T8531 program structure the dsp engine firmware performs three types of operations: 1. signal processing of the ac path data. 2. ram accesses initiated by the microprocessor interface. 3. data and program flow operations. the signal processing algorithms performed by the T8531 are implemented in firmware and are held in rom. many firmware parameters are user programmable via the microprocessor interface. interrupts from the micro- processor interface are handled once every time seg- ment (7.8 m s), and the appropriate accesses are made to the dsp engine ram registers.
lucent technologies inc. 17 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) dsp engine timing (continued) control of the dsp engine via the microprocessor interface there are four types of commands that the external controlling device may issue to the dsp engine: 1. downloading data to ram. 2. activating and deactivating lines. 3. changing the rx and tx routine to be run. 4. periodic read and/or refresh of ram space. all of these commands must only involve reading and writing to the dsp ram so that the dsp engine does not have to perform test- and branch-type operations when a microprocessor interface command is received. the complete memory map for the dsp engine ram is given in table 18. the microprocessor interface is allowed to read any ram location in the dsp engine and to write to specified addresses. the dsp engine time-slot information tables in the T8531, the dsp engine ram has been set up to contain 16 tables which hold the pointers to the ac coefficients and data buffers required to process each time slot. each table starts on a 32-word boundary and is accessed in the firmware using direct addressing instructions. each table has an rx part and a tx part (see table 18). the tables are labeled 0 through 15 and are in time-slot order, i.e., table 0 is used when processing data for time slot 0. time-slot number can vary between 0 and 15 and is used in conjunction with the card address to provide up to 64 time-slot positions on the pcm bus (see table 3). the dsp engine ac path coefficient table the microprocessor interface can control the dsp coefficients, shown in table 4. the dsp engine ram contains space to hold separate sets of coefficients for each channel, labeled channel_0 through channel_15. the coefficients are held in channel order, since they hold information that is channel specific and does not change with the time slot (see table 18). table 4 shows the ac path coefficient space for channel_0. table 4. dsp engine ram map for channel_0 ac path coefficients ram address purpose number of words initial value rgain_rel_0 rx path relative gain 1 1 (4000 h) reserved 1 rgain_abs_0 rx path absolute gain 1 1 (4000 h) tgain_abs_0 tx path absolute gain 1 1 (4000 h) bf_coef_0 balance filter coefficients 10 not initialized reserved 1 tgain_rel_0 tx path relative gain 1 1 (4000 h)
18 18 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) dsp engine timing (continued) the time-slot control word the dsp engine works in time-slot order. the tsa function is performed by the decimator/interpolator. the dsp engine is not required to reorder the data in any way. the advantages of this approach are that the group delay introduced by the tsa function is very small, and the dsp code needed for context switching is small. when the microprocessor assigns a time slot via the tsa ram, it also has to issue a new time-slot control word (tcw) instruction to the dsp engine to enable the time slot to link to the correct ac coefficients. the tcw contains the information shown in tables 5a and 5b. the tcw is only looked at when a time slot is inactive. the initial setup of the tcws assumes chan- nel-order time-slot assignment. operations performed by the dsp engine at T8531 start-up the dsp engine performs its start-up code after it has been reset. all interrupts are disabled. first, the dsp engine computes the checksum for its rom and ram to verify their integrity. next, the dsp engine walks through each time-slot information table and sets the data buffer and coefficient pointers. the dsp engine ram is set up for channel-order time-slot assignment, i.e., table 0 points to channel_0 and so on. the start-up settings for the time-slot information table (i.e., for time slot 0) are shown in table 6. the first 16 locations of ram bank 1 hold the channel address table, where pointers to the start of the coeffi- cient space for each channel are held. these pointers are set up during the start-up routine. pointers to the three sets of default coefficients are also set up. the dsp engine then walks through all 16 ac coefficient tables and sets them to their initial values as shown in the previous section. the rx and tx filter coefficients (one set for all 16 lines) are taken from rom and writ- ten to their ram locations. the dsp engine takes about 3 ms to execute the start- up code. at the end of the code, the interrupt system is enabled and the dsp engine enters sleep mode. table 5a. bit map for dsp engine time-slot control word table 5b. bit map for default per-board coefficient tables table 6. dsp engine ram map for time-slot information table 0 register bit function initial value 03 channel number channel_(time-slot number) 4go to powerup 0 5 modify coefficients 0 67 use default per-board coefficient tables 0 bit 7 bit 6 mode 0 0 do not select default tables 0 1 default table 1 coefficient set 1 0 default table 2 coefficient set 1 1 default table 2 coefficient set variable function initialized address tcw_0 time-slot control word see above rx_rtn_0 address of receive ac routine rpath_inactive tx_rtn_0 address of transmit ac routine tpath_inactive data storage reserved na
lucent technologies inc. 19 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) dsp engine timing (continued) microprocessor start-up of the dsp engine once the interrupt system is enabled, the dsp engine looks for a read or write interrupt from the microproces- sor interface once every time segment, i.e., 16 times a frame. if the ac coefficients for every channel are to be inde- pendently controlled, the microprocessor can write directly to the addresses of the 16 ac coefficient tables. this requires a total of 16 microprocessor commands to set up each channel, i.e., 16 frames to set up all 16 channels. prior to activating any time slots, the microprocessor has the option of bulk downloading the coefficients to set up the ac coefficient tables. when a channel needs to be set up and linked to its time slot, the microprocessor must send the tcw for that time slot with the modify coefficient (mc) bit (see table 5a). the mc bit causes the inactive routine for that time slot to set pointers from that time-slot space to the channel space in ram. the mc bit also causes the inactive routine to check the default coefficient bits of the tcw. if set, the appropriate default table coeffi- cients are copied over to the ram space for the chan- nel. this mechanism allows the microprocessor to download a set of coefficients that can be used by mul- tiple channels. a mix-and-match approach can be used, i.e., some channels are set up with independent sets of coeffi- cients, while other channels get a default setting. during start-up, the microprocessor must also down- load the 16 tsa commands used by the tsa block to map physical channels to time slots. this is required to initialize the tsa ram to known values. when all 16 locations have been set up, the microprocessor must send bcw2 (0x1ffc). this flags the tsa control to start normal operation. powering up a time slot in the T8531 depending on the application, the microprocessor may choose to set up the ac coefficients for a channel just prior to enabling it for use. this requires 16 micropro- cessor commands if the coefficients must be set up from scratch, or no commands if an appropriate default set has already been set up. in either case, the micro- processor must ensure that all the tx and rx parts of a channel are set up prior to enabling the time slot. if dynamic time-slot assignment is used, the micropro- cessor must next download a tsa command, which the tsa block uses to map the time slot to the required channel number. the microprocessor must enable the time slot by set- ting the go to powerup bit of the tcw. this causes the dsp engine to change the tx and rx ac routine addresses to active. a maximum of 17 commands or a minimum of one command is therefore needed to power up a channel. disabling a time slot in the T8531 to disable a time slot, the microprocessor must send a command that sets the address of either the tx or rx ac routine to tx_inactive and rx_inactive, respec- tively. the inactive routines come into use in the next tx or rx time segment for this time slot. upon returning from the inactive routine, the dsp engine checks for a microprocessor interrupt and then enters sleep mode for the rest of the time segment. t8532 powerup/powerdown each channel can be powered up independently. there are two control register addresses that can be used to control the power for each channel. in both cases, the first bit of the address word controls the power. p = 1 for powerup, and p = 0 for powerdown. one address is provided for each channel which controls the power (0x15080x150f and 0x15480x154f), and the address is followed by a data word which controls the other programmable functions for the same channel. a second address (0x15000x1507 and 0x15400x1547) is provided for each channel that controls only the power.
20 20 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) dsp engine timing (continued) changing dsp ram space of an active time slot the microprocessor is only allowed to change four ram locations for an active time slot: n relative transmit gain n relative receive gain n address of receive ac routine n address of transmit ac routine absolute gains and time-slot assignment can only be altered when the time slot is inactive. note that the dsp engine does not check the tcw of active time slots. following the initial powerup, the line card is likely to be in service without being reset for as long as it continues to operate trouble-free. therefore, the microprocessor has the option of continuously monitoring the variables it has programmed by reading them back from the dsp engine/microprocessor interface and rewriting them. dsp engine memory requirements the size of the dsp engine internal dual-port ram is 4k x 16-bit words per dsp engine. ram storage is used for user-programmable variables and for interme- diate storage of the data being processed by the device. the ram memory map is given in table 18. the on-chip rom is used for both program and data. the dsp engine firmware is rom based. the hard- ware development system code is also rom based. the dsp engine rom memory map is given in table 41. T8531 reset and start-up the chips support both hardware and software reset. hardware reset the T8531 reset functions are handled by the reset control block. hardware reset occurs if the board is powered up with rstb low. since rstb has a schmitt trigger buffer with an internal pull-up, a capacitor attached external to the rstb pin causes the pin to pull high after a specified period of time. for power-on reset, the T8531 requires that this period of time be >1 ms to give the on-chip clock synthesizer block time to start producing clock edges for the T8531 and t8532 chips (although it may not have reached its final accuracy yet). successful hardware reset of the device requires that: 1. the pcm bus signals sck and sfs should be valid at the start of the 1 ms power-on reset period. 2. v dd (and therefore rstb ) should have been low for at least 200 ms prior to commencing power-on reset to ensure that the jtag controller powerup reset cir- cuit has had time to clear the jtag controller. if, during normal operation, v dd falls below the defined minimum value, v dd min, the power-on reset procedure described above must be repeated. hardware reset occurs if rstb is pulsed high-low-high for 1 ms during normal operation (i.e., no loss of power). table 7. summary of microprocessor commands for control of T8531 data processing function required number of commands when issued bulk tsa register download & bcw2 17 start-up individual tsa register download 1 prior to activating a time slot via the tcw coefficient download 16 per channel start-up or when time slot is inactive set tcw to use/share coefficients already downloaded to default tables 1 start-up or when time slot is inactive enable time slot via tcw (fixed tsa) 1 when time slot is inactive enable time slot via tcw (dynamic tsa) 2 when time slot is inactive disable time slot 1 when time slot is active change gain value 1 per gain any time
lucent technologies inc. 21 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) T8531 reset and start-up (continued) internal reset internal reset is defined as the process that starts when the internal reset line is brought low. this happens as a consequence of hardware (rtsb ) or software (bcw1) reset. the internal reset process performs the following functions: 1. the frequency synthesizer does not receive any reset signal, and is thus unaffected by reset. follow- ing power-on reset of the T8531, the frequency syn- thesizer takes the mode determined by the scksel pin. 2. the T8531 custom logic jams all resettable latches, counters, and registers to their default values. no data is latched on any of the T8531 interfaces during internal reset. 3. the dsp engine is held in reset state. 4. the internal reset line is held low for a minimum of 18 ms to allow the frequency synthesizer to reach its final accuracy. an internal counter is started when the internal reset line goes low. it counts 80 frame sync pulses on sfs before releasing the internal reset line. 5. when the internal reset line goes high and the exm (internal) signal is held low, the dsp engine begins its start-up routine by fetching the first instruction from location 0 of the internal rom. 6. at the rising edge of the internal reset line, all the T8531 custom logic blocks commence their normal operation. reset of the t8532 devices there are two options for reset of the t8532 chips. the t8532s can make use of the same hardware reset pulse as the T8531. the T8531 supplies osck to the t8532s as soon as it is available, i.e., before the hard- ware reset has gone away. it is recommended that hardware reset be applied to all chips simultaneously. alternatively, the t8532s can be reset through software reset (tables 21 and 22), which is generated by the external controlling device and routed to the t8532s via the T8531. this can only occur when osck is guaranteed to be valid, i.e., not within 10 ms of power- on hardware reset. start-up after internal reset there is a specific sequence of microprocessor inter- face instructions that must be followed after internal reset in order to properly configure the T8531 and t8532s for normal operation. 1. if nondefault values are required, the T8531 board control word 1 (address 0x1ffe) must be updated. 2. the 16 tsa ram locations must be written before 0x1ffc. ctz must be disabled (see table 20b). 3. the all channel test register must be set for normal operation (addresses 0x1510 and 0x1550 set to 0x0004). 4. the T8531 control registers must be set. all 16 channels must be powered up (addresses 0x15000x1507 and 0x15400x1547 must be set to 0x8000). 5. the amplitude of the calibration sine wave must be set by writing address 0x0580 to coefficient 0xaa20, and address 0x0581 to coefficient 0xf49d. 6. all 16 channels must be put into initialization mode (addresses 0x15180x151f and 0x15580x155f must be set to 0x0080). 7. the dsp engine ram address 0x0002 must be set to 0x0700 to begin the first part of the t8532 cali- bration start-up sequence. 8. after 70 ms, all 16 t8532 channels must be put into loopback mode (addresses 0x15080x151f and 0x15480x154f must be set to 0x8001). 9. the dsp engine ram address 0x0002 must be set to 0x0720 to begin the second part of the t8532 calibration start-up sequence. 10. after 70 ms, both t8532s should be sent a soft reset (addresses 0x1517 and 0x1557 set to 0x8000) and the all channel test register should be set for normal operation (addresses 0x1510 and 0x1550 set to 0x0004). normal T8531 operation commences with the next sfs frame sync. the chips are now ready for channels to be enabled and filter coefficients to be set.
22 22 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable chip set functional description (continued) start-up after internal reset (continued) autocalibration autocalibration is an analog self-test and trimming pro- cedure controlled by the dsp core. sine wave signals are generated in the receive direction. these signals are looped back at the analog side of the t8532, and the return signal amplitudes are measured in the trans- mit path. this procedure provides on-the-spot fault coverage of the transmit and receive paths. it also cali- brates the octal devices by modifying the gain on each channel. channel four of the t8532 is the only channel trimmed at the factory for absolute gain accuracy. when autocalibration is run, all channels are trimmed with reference to channel four. that is, the gain on each channel is adjusted so that its absolute gain is equivalent to that of the trimmed channel. performing trimming in this manner provides channel-to-channel gain matching of better than 0.01 db. this is a much better performance than could be achieved using con- ventional trimming. trimmed values are placed in data storage, and absolute gain values are then modified accordingly any time the absolute gain register is changed. the calibration sequence measures the looped-back power result and compares it to the calibrated channel. the trim window is 0.2 db. if any channel exhibits a power value which is greater than 0.2 db, the calibra- tion procedure sets a failure flag for that channel. trim- ming will not be performed on the failed channel, and the channels trimmed gain will be left at 0 db. the failed channel, therefore, is left in its previous state and can still be used. the results of calibration are held in ram address 0x07f4 for transmit (pass 1) and 0x07f5 for receive (pass 2). a bit is set high for every failed channel. the preceding section discussed the sequence of instructions that must be followed in order to properly configure the T8531 for normal operation. the auto- calibration procedure is mandatory after hardware reset. tone plant the following tone plant functions are provided in rom code in the T8531 device. dtmf transceiver dtmf generation and detection satisfies lssgr sig- naling for analog interfaces gr-506 core, section 15. caller line identification called id transmission is performed as specified in tr- nwt-000031 (class feature: calling number deliv- ery). call progress tones a call progress tone generator is provided. this tone generator complies with telcordia * gr-506-core requirements. * telcordia is a trademark of bell communications research, inc.
lucent technologies inc. 23 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational section of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent technologies employs a human-body model (hbm) and a charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the model. no industry-wide stan- dard has been adopted for the cdm. a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely accepted and can be used for comparison. the hbm esd threshold presented here was obtained by using these circuit parameters: parameter symbol min max unit ambient operating temperature t a C40 85 c operating junction temperature t j C40 125 c thermal resistance, junction to case r q jc 35 c/w storage temperature range t stg C55 150 c power supply voltage v dd 4.75 5.25 v voltage on any pin with respect to ground v ss C0.25 5.25 v package power dissipation p d 1w hbm esd threshold device voltage (v) T8531 >1000 t8532 >1000
24 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable electrical characteristics for all specifications: t a = C40 c to +85 c, v dd = 5 v 5%, unless otherwise noted. typical values are for t a = 25 c and v dd = 5 v. input signal frequency is 1020 hz, unless otherwise noted. dsp clock frequency is 49.152 mhz. dc characteristics table 8. digital interface table 9. analog interface parameter symbol test conditions min typ max unit input voltage low v il ttl-compatible inputs 0.7 v high v ih ttl-compatible inputs 2.0 v output voltage low v ol i l = 10 ma 0.4 v high v oh i l = C10 ma 2.4 v v ohc i l = C320 m a3.5v input current pins without a pull-up or pull-down low i il gnd < v in < v il C10 m a high i ih v ih < v in < v dd 10 m a pins with a pull-up low i il gnd < v in < v il C120 C2 m a high i ih v ih < v in < v dd 10 m a pins with a pull-down low i il gnd < v in < v il C10 m a high i ih v ih < v in < v dd 2120 m a output current in high-impedance state i oz updo, sdx C40 c to 0 c C30 30 m a updo, sdx 0 c to 85 c C10 10 m a parameter symbol test conditions min typ max unit input resistance rvtx 0.25 v < vtx < 4.75 v 10 m w input resistance (dependent on the setting of the termination impedance) rvrtx 2.3 v < vrtx < 2.5 v 7 k w common-mode reference voltage vvrtx 2.2 2.4 2.6 v cmt input sink current ivrtx 2.3 v < vrtx < 2.5 v 400 m a input voltage swing vvtx 3.2 vp-p load resistance at vrp and vrn (differential) rl 4.0 k w load capacitance cl cl from vrp or vrn to v ssa 100pf output resistance ro digital input code corresponding to 0 dbm pcm code at 1.02 khz 210 w output offset voltage between vrp and vrn vos digital pattern corresponding to idle pcm code ( m -law) C100 0 100 mv output offset voltage between vrp and vrn, powerdown vospd channel powered down 10 m a max dc load C20 0 20 mv output voltage swing (differential) vrsw rl = 100 k w differential maximum receive gain 5.28 vp-p
lucent technologies inc. 25 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable electrical characteristics (continued) dc characteristics (continued) table 10. t8532 power dissipation table 11. T8531 power dissipation * powerup current exhibits a negative temperature coefficient. transmission characteristics table 12. gain and dynamic range parameter symbol test conditions min typ max unit powerdown current idd0 osck and osfs present, 8 channels powered down 912ma powerup current idd1 osck and osfs present, 8 channels powered up, normal operation 6188ma parameter symbol test conditions min typ max unit powerdown current idd0 sck and sfs present, 16 channels powered down and inactive 5060ma powerup current idd1 sck and sfs present, 16 channels powered up and active 85* 100 ma parameter symbol test conditions min typ max unit absolute levels gal maximum 0 dbm0 levels (1.02 khz): vtx (encoder milliwatt) (t8532 tx gain = 0 db; T8531 gain = C1.65 db) vrpvrn (decoder milliwatt) (t8532 rx gain = 6.02 db; T8531 gain = 0.21 db) termination impedance off 2.23 4.38 vp-p vp-p minimum 0 dbm0 levels (1.02 khz): vtx (t8532 tx gain =12.04 db; T8531 gain = C1.65 db) vrpvrn (t8532 rx gain = C12.04 db; T8531 gain = 0.21 db) termination impedance off 557.0 548.0 mvp-p mvp-p transmit gain absolute accuracy gxa transmit gain programmed for maximum 0 dbm0 test level, measured deviation of digital code from ideal 0 dbm0 level at osdx[1:0] digital outputs, with transmit gain set to 0 db: 0 c to 85 c C40 c to +85 c C0.25 C0.30 0.25 0.30 db db transmit gain variation with programmed gain gxag measured transmit gain over the range from maxi- mum to minimum, calculated deviation from the pro- grammed gain relative to gxa at 0 db: v dd = 5 v C0.1 0.1 db
26 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable transmission characteristics (continued) table 12. gain and dynamic range (continued) parameter symbol test conditions min typ max unit transmit gain variation with frequency gxaf relative to 1016 hz, minimum gain < gx < maximum gain, vtx = 0 dbm0 signal, t z = 600 w, path gain set to 0 db: f = 16.67 hz f = 40 hz f = 50 hz f = 60 hz f = 200 hz f = 300 hz to 3000 hz f = 3140 hz f = 3380 hz f = 3860 hz f = 4600 hz and above C1.8 C0.125 C0.57 C0.735 C50 C38 C44 C45 C0.5 0.04 0.01 C0.550 C9.9 C30 C26 C30 C30 0 0.125 0.125 0.015 C8.98 C32 db db db db db db db db db db transmit gain variation with signal level gxal sinusoidal test method reference level = 0 dbm0: vtx = C37 dbm0 to +3 dbm0 vtx = C50 dbm0 to C37 dbm0 vtx = C55 dbm0 to C50 dbm0 C0.25 C0.50 C1.4 0.25 0.50 1.4 db db db receive gain absolute accuracy gra receive gain programmed to 0 db, apply 0 dbm0 oversampled data to osdr0 or osdr1, measure vrp, rl = 100 k w differential: 0 to 85 c C40 c to +85 c C0.25 C0.30 0.25 0.30 db db relative gain: vrp to vrn digital input 0 dbm0 signal f = 300 hz to 3400 hz C0.01 0.01 db relative phase: vrp to vrn digital input 0 dbm0 signal f = 300 hz to 3400 hz C0.25 0.25 deg receive gain variation with programmed gain grag measure receive gain over the range from maximum to minimum setting, calculated deviation from the programmed gain relative to gra at 0 db, v dd = 5 v C0.1 0.1 db receive gain variation with frequency graf relative to 1016 hz, digital input = 0 dbm0 code, minimum gain < gr < maximum gain: 0 db path gain f = below 3000 hz f = 3140 hz f = 3380 hz f = 3860 hz f = 4600 hz and above C0.125 C0.57 C0.735 0.04 0.04 C0.550 C10.7 0.125 0.125 0.015 C8.98 C28 db db db db db receive gain variation with signal level gral sinusoidal test method, reference level = 0 dbm0: osdr = C37 dbm0 to +3 dbm0 osdr = C50 dbm0 to C37 dbm0 osdr = C55 dbm0 to C50 dbm0 C0.25 C0.50 C1.4 0.25 0.50 1.4 db db db relative termination impedance gain a t C0.2 0.2 db
lucent technologies inc. 27 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable transmission characteristics (continued) table 13. noise (per channel) * measured with a C50 dbm0 activation signal applied to vf x i input of channel under test. parameter symbol test conditions min typ max unit transmit noise, c-message weighted n xc 0 db transmit gain 18dbrnc0 transmit noise, p-message weighted n xp 0 db transmit gain C68 dbm0p receive noise, c-message weighted n rc 0 db receive gain, digital pattern corre- sponding to idle pcm code, m -law 13dbrnc0 receive noise, p-message weighted n rp 0 db receive gain, digital pattern corre- sponding to idle pcm code, a-law C75 dbm0p noise, single frequency n rs f = 0 khz to 100 khz, loop around measurement, vtx = 0 vrms C53 dbm0 power supply rejection, transmit psr x v dd = 5.0 vdc + 100 mvrms f = 0 khz to 4 khz f = 4 khz to 50 khz* c-message weighted 36 30 dbc dbc power supply rejection, receive psr r measured on vrp v dd = 5.0 vdc + 100 mvrms f = 0 khz to 4 khz f = 4 khz to 25 khz f = 25 khz to 50 khz digital pattern corresponding to idle pcm code, m -law, c-message weighted 36 40 36 dbc dbc dbc spurious out-of-band signals at the channel outputs sos 0 dbm0, 300 hz to 3400 hz input oversampled data code applied at osdr0 (or osdr1): 4600 hz to 7600 hz 7600 hz to 8400 hz 8400 hz to 50 khz C30 C40 C30 db db db
28 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable transmission characteristics (continued) table 14. distortion and group delay * varies as a function of bit offset. see appendix a. table 15. crosstalk parameter symbol test conditions min typ max unit signal to total distortion transmit or receive c-message weighted std x std r sinusoidal test method level: 3.0 dbm0 0 dbm0 33 36 db db single frequency distortion, transmit sfd x 0 dbm0 single frequency input, 200 hz f in 3400 hz; measure at any other single frequency C46 db single frequency distortion, receive sfd r 0 dbm0 single frequency input, 200 hz f in 3400 hz; measure at any other single frequency C46 db intermodulation distortion imd transmit or receive, two frequencies in the range (300 hz to 3400 hz) C55 C41 db tx group delay, absolute d xa f = 1600 hz, sck = 4.096 mhz, bit offset = 419 250* 300 m s rx group delay, absolute d ra f = 1600 hz 250 300 m s parameter symbol test conditions min typ max unit transmit to transmit crosstalk, 0 dbm0 level ct x-x f = 300 hz to 3400 hz, any channel to any channel C75 db transmit to receive crosstalk, 0 dbm0 level ct x-r f = 300 hz to 3400 hz, any channel to any other channel in-channel C75 C50 db db receive to transmit crosstalk, 0 dbm0 level ct r-x f = 300 hz to 3400 hz, any channel to any other channel in-channel C75 C50 db db receive to receive crosstalk, 0 dbm0 level ct r-r f = 300 hz to 3400 hz, any channel to any channel C75 db
lucent technologies inc. 29 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable timing characteristics a signal is valid if it is above v ih or below v il and invalid if it is between v il and v ih . for the purposes of this spec- ification, the following conditions apply: n all input signals are defined as v il = 0.4 v, v ih = 2.7 v, tr < 10 ns, tf < 10 ns. n tr is measured from v il to v ih . tf is measured from v ih to v il . n delay times are measured from the input signal valid to the output signal valid. n setup times are measured from the data input valid to the clock input invalid. n hold times are measured from the clock signal valid to the data input invalid. n pulse widths are measured from v il to v il or from v ih to v ih . table 16. pcm interface timing (see figure 9.) symbol parameter test conditions min typ max unit fsck frequency of sck (selection frequency is pin-strap programmable.) 2.048 4.096 mhz mhz tsck period of sck measured from v il to v il 1/fsck ns jitter of sck 100 ns in 100 ms = 1 ppm tschscl period of sck high measured from v ih to v ih 80 ns tsclsch period of sck low measured from v il to v il 80 ns tsch1sch2 rise time of sck measured from v il to v ih 15 ns tscl2scl1 fall time of sck measured from v ih to v il 15 ns tfshfsl period of sfs high measured from v ih to v il : 2.048 mhz 4.096 mhz 0.488 0.244 62.5 62.5 m s m s tsfhscl frame sync high setup 30 ns tsclsfl frame sync hold time 30 ns tschdxv data enabled on ts entry 0 < c load < 100 pf 0 9 90 ns tdrvscl receive data setup 30 ns tscldrx receive data hold 30 ns
30 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable timing characteristics (continued) 5-4233.a (f) * card address 0, bit offset 0 assumed. ? card address 0 assumed. notes: a is the position of the frame sync pulse in the delayed mode. b is the position of the frame sync pulse in the nondelayed mode. figure 9. timing characteristics of pcm interface assuming 2.048 mhz sck rate sfs b a tfshfsl sck 12 34 56 78910111213141516 1 123456 78 sdx * 1 sdr ? 123456 78 1 tsclsfl tsfhscl tschdxv tdrvscl tscldrx time slot 0 time slot 1 tschscl tsclsch
lucent technologies inc. 31 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable timing characteristics (continued) table 17. serial control port timing (see figure 10.) 5-4232a (f) notes: updi and upcs change at the rising edge of upck by the microprocessor and are sampled at the falling edge of upck by the dsp. updo changes at the rising edge of upck by the dsp and is sampled at the falling edge of upck by the microprocessor. figure 10. timing diagram for microprocessor write/read to/from the dsp on the control interface symbol parameter test conditions min typ max unit tcshlset upcs to upck setup 25ns tcslhhod upcs to upck hold 20 ns upck period/2 tupdist updi to upck setup 25 ns tupdihd updi to upck hold 20 ns tupdodel upck to updo delay c l = 50 pf 42 ns tupdohzdl upcs to updo high-z c l = 50 pf 34 ns tckcsh duration of upck and upcs high: write cycle read cycle 1 9 m s m s tckcsh1 duration of upck and upcs high 9 m s tcshlset tcslhhod tupdohzdl 0 131 14 15 0 131 14 15 tupdihd data (16 bits) tupdodel 0 1 132 14 15 tupdist tupdihd address (16 bits) updi updo upcs upck high-z state data (16 bits) tckcsh address tckcsh1
32 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface table 18 lists the ram data space for the dsp engine. space for up to 16 channels is allocated. the total T8531 ram size is 4 kwords, arranged as 4 x 1 kbanks. address bit 15 is used as a read/write flag (1 = read). the micro- processor interface can read any address in the dsp engine ram space. table 18. dsp engine ram memory map 1. this address can address rom code. 2. for time slots 115, the address shown is the first address. refer to time slot 0 for range information. 3. for channels 115, the address shown is the first address. refer to channel 0 for range information. address range memory contents write by microprocessor interface ram bank 0 time-slot information tables (see page 18.) 0x0000 time-slot control word (time slot 0) y 0x0001 1 receive ac routine address (time slot 0) y 0x0002 1 transmit ac routine address (time slot 0) y 0x00030x003f data storage (time slot 0) selected locations 0x0040 2 time slot 1 information table as shown for time slot 0 0x0080 time slot 2 information table as shown for time slot 0 0x00c0 time slot 3 information table as shown for time slot 0 0x0100 time slot 4 information table as shown for time slot 0 0x0140 time slot 5 information table as shown for time slot 0 0x0180 time slot 6 information table as shown for time slot 0 0x01c0 time slot 7 information table as shown for time slot 0 0x0200 time slot 8 information table as shown for time slot 0 0x0240 time slot 9 information table as shown for time slot 0 0x0280 time slot 10 information table as shown for time slot 0 0x02c0 time slot 11 information table as shown for time slot 0 0x0300 time slot 12 information table as shown for time slot 0 0x0340 time slot 13 information table as shown for time slot 0 0x0380 time slot 14 information table as shown for time slot 0 0x03c0 time slot 15 information table as shown for time slot 0 ram bank 1 ac coefficient reference tables (see page 17.) 0x04000x040f channel coefficient address table n 0x04100x0413 default coefficient address table n 0x04140x0434 reserved n ac per-channel coefficients (see page 17.) 0x0435 receive path relative gain (channel 0) y 0x0436 data storage (channel 0) n 0x0437 receive path absolute gain (channel 0) y 0x0438 transmit path absolute gain (channel 0) y 0x04390x0442 balance filter coefficients (channel 0) y 0x0443 data storage (channel 0) n 0x0444 transmit path relative gain (channel 0) y 0x0445 3 channel 1 ac filter coefficients as shown for channel 0 0x0455 channel 2 ac filter coefficients as shown for channel 0 0x0465 channel 3 ac filter coefficients as shown for channel 0 0x0475 channel 4 ac filter coefficients as shown for channel 0 0x0485 channel 5 ac filter coefficients as shown for channel 0 0x0495 channel 6 ac filter coefficients as shown for channel 0 0x04a5 channel 7 ac filter coefficients as shown for channel 0
lucent technologies inc. 33 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 18. dsp engine ram memory map (continued) 1. this address can address rom code. 2. for time slots 115, the address shown is the first address. refer to time slot 0 for range information. 3. for channels 115, the address shown is the first address. refer to channel 0 for range information. 4. per-board refers to a function that is common to all 16 channels in a single chip set. address range memory contents write by microprocessor interface ac per-channel coefficients (see page 17.) (continued) 0x04b5 channel 8 ac filter coefficients as shown for channel 0 0x04c5 channel 9 ac filter coefficients as shown for channel 0 0x04d5 channel 10 ac filter coefficients as shown for channel 0 0x04e5 channel 11 ac filter coefficients as shown for channel 0 0x04f5 channel 12 ac filter coefficients as shown for channel 0 0x0505 channel 13 ac filter coefficients as shown for channel 0 0x0515 channel 14 ac filter coefficients as shown for channel 0 0x0525 channel 15 ac filter coefficients as shown for channel 0 ac per-board 4 coefficients 0x05350x053e receive (equalizer) filter coefficients y 0x053f0x0552 transmit (equalizer) filter coefficients y 0x0553 transmit gain coefficients for filter compensation y 0x05540x055e extended receive (equalizer) filter coefficients y 0x055f0x0560 unused y default per-board 4 coefficient tables 0x0561 default table 1 receive path relative gain y 0x0562 default table 1 receive path absolute gain y 0x0563 default table 1 transmit path absolute gain y 0x05640x056d default table 1 balance filter coefficients y 0x056e default table 1 transmit path relative gain y 0x056f0x057c default table 2 coefficient set y self-test flags and tone processing 0x057d0x05ee temporary storage for self-test routines y 0x05ef0x05f3 call progress tone generation control words y 0x05f40x05fc caller id control words y 0x05fd0x05ff tone processing data storage y 0x06000x06ff tone processing time-slot tables y 0x07000x071c tone processing data storage y 0x071d0x0724 dial tone filter coefficients y 0x07250x0754 tone processing data storage y 0x0755 1 receive active routine filter address y 0x0756 1 receive inactive routine address y 0x0757 1 transmit inactive routine address y 0x07580x07ef unused y 0x07f0 result of rom checksum test n 0x07f2 result of ram checksum test n 0x07f4 result of tx path self-test n 0x07f5 result of rx path self-test n 0x07f6 rom code version number n 0x07f70x07ff unused y 0x08000x0fff caller id and dtmf data storage y
34 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 19. T8531 time-slot assignment memory map all registers can be written by the microprocessor interface. table 20a. bit map for T8531 time-slot assignment registers at 0x14000x140f table 20b. bit map for ctz disable and null channel notes: x = dont care. bits 4 and 5 default to 1 upon reset. address range memory contents 0x1400 time slot 0 channel assignment 0x1401 time slot 1 channel assignment 0x1402 time slot 2 channel assignment 0x1403 time slot 3 channel assignment 0x1404 time slot 4 channel assignment 0x1405 time slot 5 channel assignment 0x1406 time slot 6 channel assignment 0x1407 time slot 7 channel assignment 0x1408 time slot 8 channel assignment 0x1409 time slot 9 channel assignment 0x140a time slot 10 channel assignment 0x140b time slot 11 channel assignment 0x140c time slot 12 channel assignment 0x140d time slot 13 channel assignment 0x140e time slot 14 channel assignment 0x140f time slot 15 channel assignment bit number and function 156543210 not used ctz disable null channel binary-coded channel number 015 bit 5 bit 4 function x 0 disables null pointer x 1 nulls channel 0 x enables ctz 1 x disables ctz
preliminary data sheet november 2000 lucent technologies inc. 35 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 21. T8531 channel register memory map for t8532 device 0 all registers can be written by the microprocessor interface. table 22. T8531 channel register memory map for t8532 device 1 all registers can be written by the microprocessor interface. table 23. bit map for t8532 powerup/powerdown registers at 0x15000x1507 and 0x15400x1547 notes: pwr = 0: powerdown. pwr = 1: powerupnormal operation. address range memory contents 0x1500 channel 0 powerup/powerdown register 0x1501 channel 1 powerup/powerdown register 0x1502 channel 2 powerup/powerdown register 0x1503 channel 3 powerup/powerdown register 0x1504 channel 4 powerup/powerdown register 0x1505 channel 5 powerup/powerdown register 0x1506 channel 6 powerup/powerdown register 0x1507 channel 7 powerup/powerdown register 0x1508 channel 0 control register 1 0x1509 channel 1 control register 1 0x150a channel 2 control register 1 0x150b channel 3 control register 1 0x150c channel 4 control register 1 0x150d channel 5 control register 1 0x150e channel 6 control register 1 0x150f channel 7 control register 1 0x1510 all channel test register 0x1517 single-byte soft reset (no data word) 0x1518 channel 0 control register 2 0x1519 channel 1 control register 2 0x151a channel 2 control register 2 0x151b channel 3 control register 2 0x151c channel 4 control register 2 0x151d channel 5 control register 2 0x151e channel 6 control register 2 0x151f channel 7 control register 2 address range memory contents 0x1540 channel 8 powerup/powerdown register 0x1541 channel 9 powerup/powerdown register 0x1542 channel 10 powerup/powerdown register 0x1543 channel 11 powerup/powerdown register 0x1544 channel 12 powerup/powerdown register 0x1545 channel 13 powerup/powerdown register 0x1546 channel 14 powerup/powerdown register 0x1547 channel 15 powerup/powerdown register 0x1548 channel 8 control register 1 0x1549 channel 9 control register 1 0x154a channel 10 control register 1 0x154b channel 11 control register 1 0x154c channel 12 control register 1 0x154d channel 13 control register 1 0x154e channel 14 control register 1 0x154f channel 15 control register 1 0x1550 all channel test register 0x1557 single-byte soft reset (no data word) 0x1558 channel 8 control register 2 0x1559 channel 9 control register 2 0x155a channel 10 control register 2 0x155b channel 11 control register 2 0x155c channel 12 control register 2 0x155d channel 13 control register 2 0x155e channel 14 control register 2 0x155f channel 15 control register 2 bit number and function 15 140 pwr not used
36 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 24. bit map for t8532 channel control register 1 at 0x15080x150f and 0x15480x154f table 25. t8532 control register 1: transmit gain table 26. t8532 control register 1: analog termination impedance bit number and function 1514876543210 pwr not used tx gain termination impedance lpbk bit 7bit 6bit 5 mode txgain2 txgain1 txgain0 0 0 0 0 db transmit gain 0 0 1 3.01 db transmit gain 0 1 0 6.02 db transmit gain 0 1 1 9.03 db transmit gain 1 0 0 12.04 db transmit gain 1 0 1 12.04 db transmit gain 1 1 0 12.04 db transmit gain 1 1 1 12.04 db transmit gain bit 4 bit 3 bit 2 bit 1 gain (see equation on page 13.) ti3ti2ti1ti0 0000 0.0000 0001 0.0583 0010 0.1417 0011 0.2250 0100 0.3083 0101 0.3917 0110 0.5000 0111 0.5583 1000 0.6417 1001 0.7083 1010 0.8083 1011 0.8917 1100 0.9750 1101 1.0583 1110 1.2167 1111 2.0000
lucent technologies inc. 37 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 27. t8532 control register 1: digital loopback table 28. bit map for t8532 all channel test register at 0x1510 and 0x1550 table 29. bits 3:0 of t8532 all channel test register at 0x1510 and 0x1550 notes: read out address provides the previous read or write address to cdo whenever a new address is being written into the register. when analog loopback is high, data that enters the analog transmit path (vtx) is converted to a 1.024 mhz digital bit stream an d routed back to the analog receive path (vrp, vrn). the output of the transmit path is available on the oversampled data interface, but rece ive path over- sampled data is ignored. 5-5134 (f) when digital loopback is high, oversampled data receive (osdr) is routed to oversampled data transmit (osdx). the receive signa l is propa- gated to vrn/vrp, but any transmit signal from vtx is disconnected. a reference voltage on vrtx is still required in this mode. 5-5135 (f) bit 0 mode lpbk 0 normal operation 1 digital loopback bit number and function 1543210 not used read out address reserved analog loopback digital loopback bit number function 3210 0 normal operation 1 read out address 0 reserved 1 normal operation 0 normal operation 1 analog loopback 0 normal operation 1 digital loopback oversampled data interface a/d, d/a vtx vrp osdx osdr oversampled data interface a/d, d/a vtx vrp osdx osdr
38 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 30. bit map for t8532 channel control register 2 at 0x15180x151f and 0x15580x155f notes: suseq = 0: normal operation. suseq = 1: start-up calibration sequence. table 31. t8532 control register 2: receive gain table 32. T8531 control register map note: a board control word controls a function that is common to all 16 channels of a given chip set. bit number and function 158 7 63 2 1 0 not used suseq not used receive gain bit 2 bit 1 bit 0 mode tlp levels, termination impedance is on rxgain2 rxgain1 rxgain0 0 0 0 6.02 db receive gain 0 0 1 3.01 db receive gain 0 1 0 0.0 db receive gain 011 C3.01 db receive gain 1 0 0 C6.02 db receive gain 1 0 1 C9.03 db receive gain 1 1 0 C12.04 db receive gain 1 1 1 C12.04 db receive gain address range register contents write by microprocessor interface 0x1ffe board control word 1 y 0x1ffc board control word 2 y 0x1ffa board control word 3 y 0x1ff8 board control word 4 y 0x1ff6 board control word 5 y
lucent technologies inc. 39 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 33. bits 15:8 of T8531 board control word 1 at 0x1ffe table 34. bits 7:0 of T8531 board control word 1 at 0x1ffe notes: all bits in board control register 1 will be zeros upon hardware reset. in osd loopback mode, osdr0, osdr1, osdr2, and osdr3 are looped back with a delay of two osclk clock cycles to osdx0, osdx1, osdx2, and osdx3, respectively. test modes are for production testing only. m -law/a-law companding mode provides 8 bits of pcm data with the first bit (bit 1) defined as the msb and the last bit (bit 8) a s the lsb. bit 1 is the sign bit, bits 2 through 4 are the chord bits, and bits 5 through 8 are the interval bits. in linear mode, the m -law/a-law conversion in the pcm interface block is disabled and 16 bits of linear pcm data are provided. in linear mode, bit 1 is the msb and the sign bit, bit s 2 through 14 are the intervals, and bits 15 and 16 are insignificant. each interval represents 0.0001362745 vrms with 8031 intervals being the m aximum signal output of 3 dbm0. negative values are twos complement of positive values. x = dont care. bit number function 15 14 13 12 11 10 9 8 0 normal operation 1 soft reset 0 normal operation 1 tz test mode 0 normal operation 1 rx dither circuit off 0 normal operation 1 nodecim test mode 0 normal operation 1 linear mode bit number function 76543210 0 x delayed data timing 1 x nondelayed data timing x 0 x m -law x 1 0 a-law, including even bit inversion x 1 1 a-law, no even bit inversion x c1 c0 c1c0 = card address in binary x 0 reserved x 1 normal operation x 0 normal operation x 1 loopback at osd
40 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 35. bits 15:9 of T8531 board control word 2 at 0x1ffc table 36. bits 8:0 of T8531 board control word 2 at 0x1ffc note: bits 15 through 9 are not used; assumed to be zeros. bof[8:0] provide a fixed offset, relative to the frame synchronization str obe (sfs), for the first bit transmitted in each time slot. the offset is the number of data periods by which transmission of the first bi t on sdx is delayed. all subsequent transmissions also follow this offset. the default value after hardware reset or powerup is 1a3; howeve r, this reg- ister must still be written after reset. table 37. bits 15:0 of T8531 board control word 3 at 0x1ffa note: for test use only, do not use in normal operation. the default value after hardware reset or powerup is 0. table 38. bits 15:0 of T8531 board control word 4 at 0x1ff8 note: the default value after hardware reset or powerup is a4. table 39. bits 15:0 of T8531 board control word 5 at 0x1ff6 note: the default value after hardware reset or powerup is 0. table 40. bits 15:0 of T8531 reset of microprocessor commands at 0x7fff bit number and function 159 not used bit number function 8 7 6 5, 4, 3 2 1 0 bof8 bof7 bof6 bof53 bof2 bof1 bof0 bof80 = bit offset in binary bit number and function 155 40 not used tz test bits bit number and function 1510 90 not used ctz alpha coefficients bit number and function 158 70 not used ctz beta coefficients bit number function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111111111111111clear address and data words in T8531
lucent technologies inc. 41 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable software interface (continued) table 41 shows the memory map for the dsp engine rom. the rom information is not accessible via the micro- processor. the total rom size is 8 kwords. table 41. dsp engine rom memory map address range memory contents 0x0003 hds interrupt service routine 0x0008 time-slot sync interrupt service routine 0x000b start-up routine 0x0380 time segment controller (ts_proc) 0x03b0 reserved 0x03b8 reserved 0x0400 transmit path active routine 0x0500 receive path active routine 0x0503 rx path active without reading from the system interface 0x0600 transmit path inactive/loopback routine 0x0610 transmit path inactive routine 0x0680 receive path inactive/loopback routine 0x0690 receive path inactive routine 0x0700 self-test pass 1 setup (tx) 0x0720 self-test pass 2 setup (rx) 0x07a00x0b7f reserved 0x0b80 rom checker 0x0c00 ram checker 0x0e000x0f1f reserved 0x0f20 routine places tx and rx halves of a time slot into inactive loopback 0x0f30 places tx and rx halves of a time slot into inactive routine 0x0f40 routine for copying values in channel coefficient table 0 to all 16-channel tables 0x0f60 approximate location of hds code 0x0ffe checksum for rom 0x0000 : 0x07ff 0x0fff checksum for rom 0x0800 : 0x0ffd 0x1000 call progress tone generation start 0x102b call progress tone generation during operation 0x105a call progress tone generator initialization 0x10700x146f sine-wave look-up table 0x1470 caller id generation start 0x14c8 caller id generation during operation, tx path 0x1604 caller id generation during operation, rx path 0x160e caller id generator initialization 0x1650 dtmf detector start 0x16aa dtmf detector during operation subroutine 0x16fe dtmf detector during operation subroutine 0x1b3c dtmf detector initialization 0x1bd0 extended receive path active routine 0x1bd3 extended receive path active without reading from the system interface 0x1c30 extended transmit path inactive/loopback routine 0x1c37 extended transmit path inactive routine 0x1ca6 extended receive path inactive with data loopback 0x1cad extended receive path inactive routine 0x1d000x1dbb reserved 0x1cd00x1fff not used
42 42 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable applications figure 11 shows a full line card implementation using the T8531/t8532 codec and the l7585 slic with inte- grated relays. one T8531 and two t8532 devices sup- port 16 slic devices (only one l7585 slic is illustrated). figure 11 portrays only the transmission paths inside the l7585 slic. l7585 functionality includes eight solid-state relays, performing ring, test, and break functions, a ring-trip detector, quiet polarity reversal, 14 operating states, and more. for complete functionality of this slic, refer to the l7585 data sheet. the analog connection between the slic and the codec is direct; no external components are required. the transfer of control data on the octal interface between the T8531 and t8532 devices is also direct. data is synchronous with osck and transmits at a 4.096 mhz rate. the microprocessor control interface is a standard 4-wire serial port connection, micropro- cessor clock (upck), chip select (upcs ), data input (updi), and output (updo). the T8531 generates a 16 mhz clock for microprocessor use. this clock is always present. the pcm interface consists of a system clock (sck) input of either 2.048 mhz or 4.096 mhz, an 8 khz system frame sync (sfs) input, a system data transmit port (dx), and a system data receive (dr) port. the only external components required by the codec chip set are the power supply decoupling. decouple as many power supply pins as possible; at a minimum, use one capacitor per device side. 12-3351j(f) * optional for quiet reverse battery. ? 4.096 mhz operation; for 2.048 mhz operation, tie scksel to v ss . figure 11. line card solution using the l7585 slic osfs osck osdr0 osdr1 osdx0 osdx1 cdo cdi codec 0 t8532 dsp upck upcs updi updo sck sfs sdr sdx stsxb pcm bus codec 1 t8532 osdx2 osdr2 osdr3 osdx3 pcm interface control interface octal interface osdx2 osdr2 osdr3 osdx3 cdo cdi osck osfs osfs osck osdr0 osdr1 osdx0 osdx1 cdi cdo ccs0 ccs1 ccs0 ccs1 dgnd vccd rdo rsw rts pr pt rti tti clk vsp vbat bgnd vcca agnd ndet ncs b5 b4 b3 b2 b1 b0 fb1 fb2 cf1 cf2 dcr dcout iprog lcth rcvn rcvp vtx vrtx txi vitr itr relay k1 cvd 0.1 m f crtf 0.1 m f rs1* 400 w rrtf 1 m w 260 v surge protector rpr 82.5 w rpt 82.5 w test-in bus 1 mhz clock battery back ringing cvb 0.1 m f C48 v cva 0.1 m f +5 v +10 v fb2* cf1 0.22 m f cf2 0.1 m f rprog 64.9 k w rlcth 24.9 k w +5 v cb1 0.1 m f slic 0 l7585 parallel data bus to microprocessor 0.1 m f +5 v 0.1 m f +5 v rstb scksel ? rstb 0.1 m f0.1 m f channels 815 channels 17 +5 v +5 v channel 0 vrn0 vrp0 vtx0 vrtx0 test test vddd rstb rstb rstb ck16 vss +5 v 0.1 m f vdd 2.4 v rgx1 8.25 k w tip ring 0.047 m f fb1* 0.047 m f vdda vssa vddd vssd vdda vssa vddd vssd micro- processor asic 100 v 100 v 100 v 100 v 10 v 50 v 100 v trng rrng earth back ringing trng rrng trng rrng ringing bus (see below) 100 v T8531
lucent technologies inc. 43 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable applications (continued) figure 12 shows the complete slic schematic for interfacing to the lucent l9215g short-loop, sine wave, ringing slic. all ac parameters are programmed by the codec. note this codec differentiates itself in that no external com- ponents are required in the ac interface to provide a dc termination impedance or for stability. for illustration pur- poses, 0.5 vrms ppm injection was assumed in this example and no meter pulse rejection is used. also, this example illustrates the device using programmable overhead and current limit. the components associated with v ref can be replaced by a common voltage reference circuit (see figure 14). 12-3534c (f) figure 12. line card solution using the l9215g slic v bat1 bgnd v bat2 v cc agnd icm trgdet ground key not used c bat1 0.1 m f c bat2 0.1 m f c cc 0.1 m f rtflt dcout pr pt ovh v prog v ref c rt 0.1 m f r rt 383 k w lucent l7591 v bat2 fusible or ptc 50 w 50 w cf1 cf2 rate of battery reversal not ramped fb1 fb2 nstatbrb2b1b0 c f1 0.47 m f c f2 0.1 m f ppm 0.5 vrms c ppm 10 nf ring in ppm in vitr r cvp r cvn itr vtx txi r gx 4750 w v bat1 d bat1 v bat2 v cc c tx 0.1 m f c ring 0.47 m f not used from programmable d/a voltage source c c1 t8532 vtx vrp vrn l9215g from/to control 0.1 m f fusible or ptc c vref vrtx v cc r vref2 4.32 k w r vref1 4.02 k w 301 k w r vref3 10 v 10 m f
44 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable applications (continued) figure 13 shows the complete slic schematic for interfacing to the lucent l9310g line interface and line access circuit. all ac parameters are programmed by the codec. note this codec differentiates itself in that no external components are required in the ac interface to provide a dc termination impedance or for stability. for illustration purposes, 2.2 vrms ppm injection was assumed in this example and hybrid meter pulse rejection is used. also, this example illustrates the device using the battery switch with multiple battery operation and programmable overhead, current limit and loop closure threshold. 0500 (f) figure 13. line card solution using the l9310g slic r s1 fusible 50 w cv bat1 0.1 m f v bat1 rts v prog (i limit = 25 ma) lcth (threshold = 11 ma) v bat c f2 0.1 m f fb2 cf1 vtx itr ppmout c rts 0.1 m f ppmin agnd v dd 1 m w 50 w r ring 100 v130 v secondary or ptc fusible or ptc r rtf 400 w ringing source c cc 0.1 m f v cc c dd 0.1 m f v dd ad c tx 0.1 m f r gx 6.49 k w rsw pt v bat2 /v cc bgnd v bat1 trgdet icm dgnd txi txn protector 180 v330 v secondary protector fb1 v ref testlev testsig cf2 per-line to/from microprocessor v bat2 cv bat2 0.1 m f c ppm 0.01 m f r ppm 17.4 k w ramped ppm generation 0.7 vrms for 2.2 vrms at t/r ovh (overhead = 9.2 v for 2.2 vrms ppm) from programmable voltage source pwr t ring l9310g (gain of 2) lcf pr reset r lcth vitr r cvp r cvn c c1 t8532 vtx vrp vrn 0.1 m f vrtx 301 k w r vref v ref
lucent technologies inc. 45 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable applications (continued) common voltage reference every channel of the t8532 codec requires a 2.4 v ref- erence (vrtx) for operation. some slics provide this reference for the codec. an external circuit is required for slics without the reference voltage. figure 14 shows a circuit that can provide the 2.4 v ref- erence for 16 or more channels. even with the com- mon reference voltage, interchannel crosstalk remains insignificant. the circuit employs a single supply op amp as a voltage follower. r1 and r2 set up the refer- ence voltage. rl provides a reference bias when all channels are programmed off and provides a dis- charge path for the reference filtering. the op amp s upplies an ample minimum of 20 ma. each channels vrtx node only requires a maximum of 340 m a, and vtx is a high-impedance input. the r vrefx resistors provide the necessary bias for the vtx inputs. 12-3570 (f)x figure 14. common 2.4 v voltage reference 2.15 k w r2 2.37 k w r1 0.1 m f 10 m f 5 v 3 2 C + 5 v 8 4 1 1/2 lm2904 or 1.91 k w rl 0.1 m f 10 m f equivalent vrtx15 vrtx1 vrtx0 vtx0 vtx1 vtx15 to T8531/2 r vref15 301 k w r vref1 301 k w r vref0 301 k w + +
46 lucent technologies inc. preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable outline diagrams 64-pin mqfp 5-5202(f) 33 48 14.00 0.20 17.20 0.25 detail a detail b 3.00 max 0.80 typ seating plane 0.10 2.55/2.75 0.25 max 1 16 49 64 pin #1 identifier zone 17.20 0.25 14.00 0.20 32 17 0.30/0.45 0.16 m 0.13/0.23 detail b 0.25 0.73/1.03 1.60 ref gage plane seating plane detail a
lucent technologies inc. 47 preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable outline diagrams (continued) 64-pin tqfp 5-3080 (f) detail a 0.50 typ 1.60 max seating plane 0.08 detail b 0.05/0.15 1.40 0.05 10.00 0.20 12.00 0.20 1 64 49 16 17 32 48 33 10.00 0.20 12.00 0.20 pin #1 identifier zone detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 detail b 0.19/0.27 0.08 m 0.106/0.200
preliminary data sheet november 2000 codec chip set T8531/t8532 multichannel programmable l u cent t e chnolo g ies inc . res e rves t he r i g ht t o mak e cha n ges t o th e pro d uct(s ) o r info r matio n cont a ined h erei n withou t notice . n o liabilit y i s assu m ed as a r esult o f thei r use or a pplicatio n . no r ights u n der a ny pa t ent acc o mpa n y the s a le of a ny such p rod u ct(s ) or in f orm a tion. co p yrigh t ? 200 0 luce n t t echn o logies i n c. all rights res e rved nove m ber 2000 ds01 - 028alc (replaces d s 00-379 a lc) f o r a d d i ti o n a l i n fo r m a t i o n , c o n ta c t y o u r m i c r o e l e c t r o n i c s g r o u p a cc o u n t m a n a ge r o r t h e f o l l o wi n g: i n terne t : http://ww w .lucent.com/micro e-m a il: do c m a ste r @mi c ro . luc e nt.com n . a m e r ic a : m i c r o e l e c t r o n i cs g r o u p, l u c e nt t e c hn o l o g i e s i n c ., 5 5 5 u n i o n b o u l e v a r d , r o o m 3 0 l - 1 5 p - b a , a l l e nt o wn , p a 1 8 1 0 9 - 3 2 86 1 - 80 0 - 37 2 - 2 4 4 7 , f a x 6 1 0 - 7 1 2 - 4 10 6 ( i n c a n a d a : 1 - 8 0 0 - 5 5 3 - 2 44 8 , f a x 6 1 0 -7 1 2 - 4 1 0 6 ) a s i a p a cif i c : m i c r o e l e c t r o n i cs g r o u p, l u c e nt t e c hn o l o g i e s s i ng a p o r e p t e . l t d., 7 7 s c i e n c e p a r k d r i v e, #0 3 - 1 8 c i nt e c h i i i, s i n g a p o r e 1 1 8 2 56 t el . ( 6 5 ) 77 8 8 83 3 , f a x ( 6 5 ) 7 7 7 74 9 5 c h i n a: m i c r o e l e c t r o n i cs g r o u p, l u c e n t t e c h n o l og i e s ( c h i na ) c o., l td . , a - f 2 , 2 3 / f , za o fo n g u n i v e r s e b u i l d i n g , 1 8 0 0 zh o ng s h an x i r o a d , s h a n g h ai 2 00 2 3 3 p . r. ch i na t e l . ( 8 6 ) 2 1 6 4 4 0 0 4 6 8 , e x t . 3 2 5 , f a x ( 86 ) 21 64 4 0 06 5 2 j a p a n : m i cr o e l e c t r o n i cs g r o u p, l u c e nt t e c hn o l o g i e s j a pa n l t d., 7 - 1 8 , h i g a s h i - got a n d a 2 - c h o m e, s h i n a g aw a - k u , t o k y o 1 4 1, j a p a n t e l . ( 8 1) 3 5 4 21 1 60 0 , f a x ( 8 1 ) 3 5 4 2 1 17 0 0 e u r op e : d at a r e qu e s t s : m ic r o e l e ct r oni c s g r ou p d a t a l i n e : t el . ( 44 ) 70 0 0 5 8 2 3 6 8 , f a x ( 44 ) 1 1 8 9 3 2 8 1 48 t e c h n i c a l in q u i r i e s : g e r ma n y : ( 4 9 ) 89 9 5 0 8 6 0 (munich ) , united kingdom: ( 4 4 ) 1 3 4 4 8 6 5 9 0 0 ( a scot) , f r a n ce: ( 3 3 ) 1 4 0 8 3 6 8 0 0 (p a r i s), s we d e n : ( 4 6) 8 5 9 4 6 07 00 (stockholm), f inl a nd: ( 3 5 8 ) 9 3 5 0 76 7 0 (h e ls i n k i), i t a l y : ( 3 9 ) 0 2 6 6 0 8 13 1 (m i l a n ) , s p a i n : ( 3 4 ) 1 8 0 7 1 4 4 1 (madrid) ordering information appendix a. t r ansmit path group delay vs. bit offset receive pa t h gro u p d e l a y is a fix e d value a nd is s p ecifie d i n the d ata s h eet. note : bit o f fse t valu e s f or partial ti m e seg m en t s w ould incr e me n tally add t o the b ase d ata d elay v a lue by 4 8 8 ns per b it o f f set for an s c k o f 2. 0 48 m hz and in i n cre m ents o f 2 4 4 ns p e r bit o f fs e t f o r a n sc k of 4 .096 mhz. t able 42. t rans m it path group dela y vs . bit offset device code package t emperature comcode t - 8 531 - - - t l - d b 6 4 - p i n t q f p , d r y p a c k t r a y C 40 c t o +85 c 1 08 6 97 7 07 t -85 3 1 - - - tl-dt 6 4 -pin tqf p , d ry-ba g ge d , t ap e & r e el C 40 c t o +85 c 1 08 5 56 6 14 t -8 5 32 - - - jl-db 6 4 -pin mqf p , dr y pack tray C 4 0 c t o +85 c 1 08 6 97 3 01 t - 8 532 - - - jl-tr 6 4-pin m qf p , t a p e & re e l C 40 c t o +85 c 1 08 5 56 6 30 bi t offse t in whole t ime segments bit o f fset sck = 2 . 048 mhz bit offset sck = 4 . 096 mhz t x data d elay (s) f = 1600 hz 0 0 0 2 7 3.4 1 1 6 3 2 2 8 1 . 2 2 3 2 6 4 2 8 9 . 0 3 4 8 9 6 2 9 6 . 8 4 64 128 3 0 4.6 5 80 160 3 1 2.4 6 96 192 3 2 0.2 7 1 12 224 3 2 8.0 8 128 256 3 3 5.8 9 144 288 3 4 3.6 10 160 320 3 5 1.4 1 1 176 352 3 5 9.2 12 192 384 3 6 7.0 13 208 416 2 5 0.0 14 224 448 2 5 7.8 15 240 480 2 6 5.6

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